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5-22-2 LOGICAL AND – ANDW(34)
I1: Input 1
IR, SR, AR, DM, HR, TC, LR, #
I2: Input 2
IR, SR, AR, DM, HR, TC, LR, #
Ladder Symbols
Operand Data Areas
R: Result word
IR, SR, AR, DM, HR, LR
ANDW(34)
I1
I2
R
@ANDW(34)
I1
I2
R
Description When the execution condition is OFF, ANDW(34) is not executed. When the ex-
ecution condition is ON, ANDW(34) logically AND’s the contents of I1 and I2
bit-by-bit and places the result in R.
10 0110 0110 0110 01
15 00
01 0101 0101 0101 01
00 0100 0100 0100 01
15 00
15 00
I1
I2
R
Flags ER: Indirectly addressed DM word is non-existent. (Content of :DM word is
not BCD, or the DM area boundary has been exceeded.)
EQ: ON when the result is 0.
Example
Logic Instructions Section 5-22
- Programmable Controllers 1
- Operation Manual 2
- OMRON Product References 3
- Visual Aids 3
- About this Manual: 4
- TABLE OF CONTENTS 5
- Table of contents 11
- PRECAUTIONS 13
- 1 Intended Audience 14
- 2 General Precautions 14
- 3 Safety Precautions 14
- 5 Application Precautions 15
- Conformance to EC Directives 16
- Section 6 16
- SECTION 1 17
- Introduction 17
- 1-1 Overview 18
- 1-2 The Origins of PC Logic 18
- 1-3 PC Terminology 19
- 1-4 OMRON Product Terminology 19
- 1-5 Overview of PC Operation 20
- 1-6 Peripheral Devices 21
- 1-7 Available Manuals 21
- 1-8 New C200HS Features 22
- 1-8-2 Faster Execution Times 23
- 1-8-3 Larger Instruction Set 24
- 1-8-11 Peripheral Devices 26
- 1-8-12 Using C200H Programs 27
- Memory Cassette to the CPU 29
- SECTION 2 30
- Hardware Considerations 30
- 2-1 CPU Components 31
- 2-1-1 CPU Indicators 32
- 2-2 PC Configuration 33
- 2-4 Memory Cassettes 36
- Metal bracket 37
- 2-6 CPU DIP Switch 38
- SECTION 3 39
- Memory Areas 39
- 3-1 Introduction 40
- 3-2 Data Area Structure 41
- 3-8 TC Area 42
- 3-3 IR (Internal Relay) Area 45
- IR Area Section 3-3 46
- 3-4 SR (Special Relay) Area 47
- SR Area Section 3-4 48
- 3-4-2 Remote I/O Systems 53
- Host Link Systems 54
- PC Link Systems 54
- 3-4-4 Forced Status Hold Bit 55
- 3-4-5 I/O Status Hold Bit 56
- 3-4-6 Output OFF Bit 56
- 3-4-8 Low Battery Flag 56
- 3-4-9 Cycle Time Error Flag 57
- 3-4-11 First Cycle Flag 57
- 3-4-12 Clock Pulse Bits 57
- 3-4-13 Step Flag 58
- 3-4-14 Group-2 Error Flag 58
- 3-4-17 Arithmetic Flags 58
- 3-4-21 Memory Cassette Areas 60
- 3-4-24 Memory Error Flags 61
- 3-4-25 Data Save Flags 61
- 3-4-26 Transfer Error Flags 62
- 3-4-27 PC Setup Error Flags 62
- AR Area Section 3-5 63
- 3-5-2 Slave Rack Error Flags 64
- 3-5-3 Group-2 Error Flags 64
- 3-5-6 Error History Bits 65
- 3-5-7 Active Node Flags 66
- 3-5-10 TERMINAL Mode Key Bits 67
- :DM 0100 69
- RESETSET 70
- EXT MONTR 70
- 3-6-3 Error History Area 71
- DM Area Section 3-6 73
- 3-7 HR (Holding Relay) Area 74
- 3-8 TC (Timer/Counter) Area 74
- 3-9 LR (Link Relay) Area 75
- 3-10 UM Area 75
- SECTION 4 76
- 4-1 Basic Procedure 77
- 4-2 Instruction Terminology 77
- 4-3 Program Capacity 78
- 4-4 Basic Ladder Diagrams 78
- Instruction 79
- 00000 00100 LR 0000 81
- 4-4-4 OUTPUT and OUTPUT NOT 83
- 4-4-5 The END Instruction 83
- 00000 00001 85
- 4-5 The Programming Console 91
- 4-6 Preparation for Operation 93
- 4-6-1 Entering the Password 94
- 4-6-2 Buzzer 94
- 4-6-3 Clearing Memory 95
- 4-6-5 Clearing Error Messages 98
- 4-6-6 Verifying the I/O Table 99
- 4-6-7 Reading the I/O Table 100
- Meaning of Displays 101
- 4-6-8 Clearing the I/O Table 102
- 4-7-3 Checking the Program 109
- 4-8 Controlling Bit Status 110
- Section 5 Instruction Set 110
- 4-7-5 Program Searches 112
- Original Program 114
- Diagram A: Correct Operation 116
- 5-10 INTER 119
- 4-7-8 Jumps 120
- 4-8-2 KEEP 122
- 00002 00003 123
- 00004 00005 123
- Work Bits Section 4-9 124
- 4-10 Programming Precautions 125
- AND LOAD and OR LOAD 126
- 4-11 Program Execution 127
- SECTION 5 128
- Instruction Set 128
- 5-1 Notation 131
- 5-2 Instruction Format 131
- ∗DM 0001 132
- 5-5 Expansion Instructions 133
- Section 4 Writing 135
- 5-7 Instruction Set Lists 138
- 4-4-3 Ladder Instructions 142
- 5-9 Bit Control Instructions 143
- IR, AR, HR, LR 144
- 5-23 Subroutines and Inter 145
- 5-9-4 KEEP – KEEP(11) 146
- 4-8-3 Self-maintain 147
- 5-10 INTERLOCK – 147
- 5-14-1 TIMER – TIM 148
- N: Jump number 150
- # (00 to 99) 150
- 5-12 END – END(01) 151
- 5-13 NO OPERATION – NOP(00) 151
- 5-14-4 COUNTER – CNT 153
- 5-14-4 COUNTER 154
- 5-9-4 KEEP – 154
- KEEP(11) 154
- N: TC number 156
- # (000 through 015 preferred) 156
- SV: Set value (word, BCD) 156
- IR, AR, DM, HR, LR, # 156
- # (000 through 511) 161
- 5-15 Data Shifting 163
- Data Shifting Section 5-15 164
- 5-15-5 ROTATE LEFT – ROL(27) 168
- 5-15-6 ROTATE RIGHT – ROR(28) 168
- 5-15-9 WORD SHIFT – WSFT(16) 170
- ASFT(17) 171
- 5-16-1 MOVE – MOV(21) 172
- 5-16-2 MOVE NOT – MVN(22) 172
- 5-16-3 BLOCK SET – BSET(71) 173
- Data Movement Section 5-16 174
- DIST(80) 176
- IR, SR, AR, DM, HR, TC, LR, # 177
- COLL(81) 179
- 5-16-9 MOVE DIGIT – MOVD(83) 180
- XFRB(62) 182
- MCMP(19) 183
- Data Comparison Section 5-17 184
- BCMP(68) 188
- TCMP(85) 189
- 5-18 Data Conversion 193
- Data Conversion Section 5-18 194
- @HEX(––) 211
- LINE(63) 213
- COLM(64) 214
- 5-19 BCD Calculations 217
- 5-19-3 SET CARRY – STC(40) 218
- 5-19-4 CLEAR CARRY – CLC(41) 218
- 5-19-5 BCD ADD – ADD(30) 218
- BCD Calculations Section 5-19 219
- 5-19-7 BCD SUBTRACT – SUB(31) 220
- 5-19-9 BCD MULTIPLY – MUL(32) 224
- 5-19-11 BCD DIVIDE – DIV(33) 225
- 5-20 Binary Calculations 232
- Mi – Su – CY CY R 234
- MBSL(––) 244
- DBSL(––) 246
- 5-21-2 FIND MINIMUM – MIN(––) 247
- 5-21-4 SUM – SUM(––) 250
- @SUM(––) 252
- Examples 253
- 5-21-6 PID CONTROL – PID(––) 255
- 1, 2, 3 261
- 5-22 Logic Instructions 262
- 5-22-2 LOGICAL AND – ANDW(34) 263
- 5-22-3 LOGICAL OR – ORW(35) 264
- 5-23-1 Subroutines 266
- 5-23-2 Interrupts 267
- Interrupt mode 268
- (1 = high-speed) 268
- N: Subroutine number 270
- 00 to 99 270
- 5-23-5 MACRO – MCRO(99) 273
- 3-6-4 PC Setup 276
- 5-24 Step Instructions 279
- Step controlled by LR 2000 280
- Step controlled by LR 2001 280
- 5-25 Special Instructions 288
- 5-25-2 CYCLE TIME – SCAN(18) 289
- LSS Operation Manual 290
- Appendix 291
- FAL(06) 00 292
- TERM(48) 294
- 6-1 Cycle Time 295
- 00000 00002 299
- 00001 00003 299
- Diagnostic 299
- @SRCH(––) 303
- @XDMR(––) 304
- SEND(90) 305
- Control Data 306
- RECV(98) 307
- SYSMAC LINK System Manual 308
- SEND(90)/RECV(98) Enable Flag 309
- SEND(90)/RECV(98) Error Flag 309
- 5-27-1 RECEIVE – RXD(––) 310
- 5-27-2 TRANSMIT – TXD(––) 312
- 0123456789101112 316
- Input Unit 322
- Output Unit 322
- 5-28-5 MATRIX INPUT – MTR(––) 326
- B0B1B2B3B4B5B6B7B8B9 327
- A0A1A2A3A4A5A6A7A8A9 327
- A0A1A2A3A4A5A6A7A8 327
- SECTION 6 329
- Program Execution Timing 329
- Cycle Time Section 6-1 331
- 6-3 Instruction 332
- Execution Times 332
- 6-2 Calculating Cycle Time 334
- 6-2-2 PC with Link Units 335
- ÷ constant → word 339
- ÷ word→ word 339
- ÷ :DM → :DM 339
- ÷ word → word (equals 0) 341
- 6-4 I/O Response Time 345
- 6-4-2 Remote I/O Systems 346
- RT + TTT 347
- 6-4-3 Host Link Systems 348
- PC Link Unit 349
- I/O Response Time Section 6-4 350
- SECTION 7 356
- 7-1-1 Bit/Word Monitor 357
- 7-1-2 Forced Set/Reset 360
- 7-1-3 Forced Set/Reset Cancel 362
- Word currently 363
- [ Data ] 363
- 7-1-8 Differentiation Monitor 368
- 7-1-9 3-word Monitor 369
- 7-1-11 Binary Monitor 370
- Indicates Force Reset 371
- Indicates Force Set 371
- (Force Status Clear) 372
- IR bit 00115 IR bit 00100 373
- Returns to original display 375
- Current SV (during 375
- SV before the change 375
- 7-1-15 UM Area Allocation 377
- 7-1-18 Keyboard Mapping 379
- SECTION 8 383
- Communications 383
- 8-1 Introduction 384
- Section 8-2 385
- 8-2-3 Wiring Ports 387
- 00100 SR 26405 389
- 8-2-7 NT Links 394
- SECTION 9 395
- Memory Cassette Operations 395
- 9-1 Memory Cassettes 396
- 9-3 UM Area Data 397
- 9-4 IOM Area Data 398
- IOM Area Data Section 9-4 399
- SECTION 10 400
- Troubleshooting 400
- 10-1 Alarm Indicators 401
- 10-4 Error Messages 401
- Error Messages Section 10-4 402
- Remote I/O 403
- Master Unit number 403
- Rack no 404
- 10-5 Error Flags 406
- Error Flags Section 10-5 407
- 10-6 Host Link Errors 408
- SECTION 11 409
- Host Link Commands 409
- 11-1 Communications Procedure 410
- Command and Response Formats 412
- Section 11-2 412
- 11-2-2 Commands from the PC 414
- 11-3 Host Link Commands 415
- 11-3-3 HR AREA READ –– RH 416
- 11-3-4 PV READ –– RC 416
- 11-3-5 TC STATUS READ –– RG 417
- 11-3-6 DM AREA READ –– RD 417
- 11-3-7 AR AREA READ –– RJ 418
- 11-3-8 IR/SR AREA WRITE –– WR 418
- 11-3-9 LR AREA WRITE –– WL 419
- 11-3-10 HR AREA WRITE –– WH 419
- 11-3-11 PV WRITE –– WC 420
- 11-3-12 TC STATUS WRITE –– WG 420
- 11-3-13 DM AREA WRITE –– WD 421
- 11-3-14 AR AREA WRITE –– WJ 421
- 11-3-15 SV READ 1 –– R# 422
- 11-3-16 SV READ 2 –– R$ 423
- 11-3-17 SV READ 3 –– R% 424
- 11-3-18 SV CHANGE 1 –– W# 425
- 11-3-19 SV CHANGE 2 –– W$ 425
- 11-3-20 SV CHANGE 3 –– W% 426
- 11-3-21 STATUS READ –– MS 427
- 11-3-22 STATUS WRITE –– SC 428
- 11-3-23 ERROR READ –– MF 429
- 11-3-24 FORCED SET –– KS 430
- 11-3-25 FORCED RESET –– KR 431
- Section 11-3 432
- 11-3-28 PC MODEL READ –– MM 433
- 11-3-29 TEST–– TS 434
- 11-3-30 PROGRAM READ –– RP 434
- 11-3-31 PROGRAM WRITE –– WP 435
- 11-3-34 ABORT –– XZ 437
- 11-3-35 INITIALIZE –– :: 438
- 11-4 Host Link Errors 439
- Appendix A 440
- C200H Standard I/O Units 441
- C200H Special I/O Units 442
- C200H Link Units 443
- Optional Products 444
- Link Adapters 445
- Appendix AStandard Models 446
- Standard Models Appendix A 447
- Programming Devices 448
- Training Materials 448
- Appendix B 449
- Expansion Instructions 452
- Appendix C 455
- Appendix D 459
- Appendix DMemory Areas 460
- DM Area (Error Log) 465
- Appendix E 466
- Appendix EPC Setup 467
- Appendix F 470
- I/O Bits 471
- Work Bits 472
- Data Storage 473
- Timers and Counters 474
- Appendix G 475
- Program Coding Sheet 476
- Appendix H 477
- Signed Binary Data 478
- Space 0 @ P ‘ p 0 @ P ‘ p 479
- Glossary 480
- Revision History 496
- TTIM(120): 5−1 to 5−14 145 504
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